IBX PCMCIA 'port'

[Vincent Sanders]

Sorry ive been a bit busy to reply lately :-)

On Tue, Feb 12, 2002 at 12:03:16AM +0000, Adrian Godwin wrote:
> >
> > Whilst it is true that the PCMCIA port is not a full PCMCIA
> > implementation, it possible that this might still be a useful port. In
> > particular, it would not be too difficult to get linear flash ROM cards
> > to work on this port IMHO. I have a few linear flash cards that I use on
> > my Newton that I intend to try...
> >

Please be careful, i have destroyed a memory card - hence my previous comments
on magic smoke..

> > I am sure that the unfitted 68-pin connector is intended for a PCMCIA
> > socket. Most of the signals to this PCMCIA socket are unbuffered and
> > shared for other functions in the bush box. 

Oh yes its a pcmcia socket all right but it was only ever intended for use
a replacement roms, all this design came from when online media/art etc 
produced an nci (network computer) reference design. The bush box looks
suspiciously like a re-hash of that design.

> 
> A hunt around Google suggests that it might be the socket used on
> the NC for expansion ROMs, and that they might replace rather than
> supplement the internal ROMs. But I can't find any details of how
correct
> those ROMs are wired.
>

Neither can I :-) and i have acess to an original nci design....

> > However, ss long as you power up tghe IBX with a PCMCIA card already
> > installed, and only remove the PCMCIA when switched off, you should be
> > OK. Plugging in a PCMCIA whilst powered on might cause the IBX to crash
> > (and burn?) - as the data and address lines are not buffered (unless
> > PCMCIA cards take care of this???).

Dont think so...

> >
> > PCMCIA (or PC Card) socket appears to have GND and 5v power wired
> > correctly. 16-bit data is taken from the main ARM 32-bit data bus D0-D15
> > (also shared by the operating system ROMs). Latched address bus LA2-LA23
> > is connected to PCMCIA A0-A21 as expected. PCMCIA A21 and above are
> > connected to some of the top data lines (i.e. ARM  D16-D31). Some other
> > control pins are also connected to these top 16 data lines. Using the
> > top 16 bits of the 32-bit data bus as a sort of control 'register' for
> > the PCMCIA port should not be a problem.
as shown in my box i run from a signgle 16bit macronix eeprom so they only need
D0-D15 and they limited the available space on these external rom cards
to 4megs
> 
> How would you set the top 16 bits on a read cycle ? Write is easy enough ..
> 
> >
> > Does anybody know for sure what the original plan for this PCMCIA socket
> > was ? Does anybody have a copy of the RiscOS PCMCIA module ?
> 
> >From the earlier comment it sounds as though they started with PCMCIA
> and then changed some things (perhaps a cost reduction), so it might
> need some serious bodging.
> 
It was a convenient socket, the earlier versions appear to have the power 
conencted wrong which later versions fixed to make it "compatible" just be 
careful.
> 
> Some other possibilities :
> 
> ZIP PPA is SCSI via a parallel port adapter. ATA is SCSI command set via 
> an IDE interface. So maybe it's feasible to make something that adapts
> the parallel port zip connection onto something more modern, like an
> IDE disk or a compact flash.
> 
> The FDC37C699 has a mode where it accesses a floppy via the parallel
> port pins. This bizarre idea is intended for use on a laptop, where
> an optional floppy connects to the parallel port. I think the A4
> used such a chip, though I don't remember whether RISCOS supported it. 

it doesnt but a driver might be written

> 
> There's a RAM filing system on the box, called cachefs. You have to
> configure it to have some size (see 'help cachefs'), then you can 
> write to it (cache:$). This gives somewhere to load a module from 
> without mass storage, if you can get the module on there. This might 
> be possible using the web browser (does it cache pages in cache: ?) 
> or the webftp module (if anyone knows how to work it).
> 
> You can reset the box without power cycling it by shorting pins
> 5 (reset) and 6(ground) of LK5. I'm not sure yet if this provides
> a soft 'break'-like function, but it's likely to be less destructive
> to ram contents than power cycling.
> 
err um this is the hardware reset line, I cant remember off hand if it removes
the dram refresh or not. It certianly resets teh rest of the system back
to por mode
> 
> -adrian
> 
> 

Regards Vincent